M24C02-RBN3TPSLASHS datasheet(13/39 Pages) STMICROELECTRONICS

13 / 39 page

M24C16, M24C08, M24C04, M24C02, M24C01

Device operation

Doc ID 5067 Rev 16

13/39

Figure 7.

Write mode sequences with WC = 1 (data write inhibited)

3.6

Write operations

Following a Start condition the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an

address byte. The device responds to the address byte with an acknowledge bit, and then

waits for the data byte.

When the bus master generates a Stop condition immediately after a data byte’s Ack bit (in

the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal write

cycle is triggered. A Stop condition at any other time slot does not trigger the internal write

cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and

the device does not respond to any requests.

3.6.1

Byte Write

After the device select code and the address byte, the bus master sends one data byte. If

the addressed location is Write-protected, by Write Control (WC) being driven High (during

the period from the Start condition until the end of the address byte), the device replies to

the data byte with NoAck, as shown in Figure 7, and the location is not modified. If, instead,

Byte Write

Dev select

Byte address

Data in

Page Write

Dev select

Byte address

Data in 1

Data in 2

Data in 3

AI02803d

Page Write

(cont'd)

WC (cont'd)

Data in N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

M24C02-RBN3TP/S Datasheet(PDF) 13 Page - STMicroelectronics

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