M24C02-RBN5TPSLASHS datasheet(16/39 Pages) STMICROELECTRONICS

16 / 39 page

Device operation

M24C16, M24C08, M24C04, M24C02, M24C01

16/39

Doc ID 5067 Rev 16

Figure 10.

Read mode sequences

The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must

be identical.

3.7

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

The device has an internal address counter which is incremented each time a byte is read.

3.7.1

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 10) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

Dev select *

Byte address

Dev select

Data out 1

AI01942b

Data out N

Current

Address

Read

Dev select

Data out

Random

Address

Read

Dev select *

Data out

Sequentila

Current

Read

Data out N

Dev select *

Byte address

Sequential

Random

Read

Dev select *

Data out 1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

M24C02-RBN5TP/S Datasheet(PDF) 16 Page - STMicroelectronics

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