P9S12XEP100J1VVLR datasheet(79/1324 Pages) FREESCALE

79 / 1324 page

Chapter 1 Device Overview MC9S12XE-Family

MC9S12XE-Family Reference Manual Rev. 1.21

Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

1.4.2.4

XGATE Fake Activity Mode

This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread

and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled

peripherals continue to function.

1.4.2.5

Wait Mode

This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in

system wait mode. For further power consumption the peripherals can individually turn off their local

clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked and is not routed to XGATE

ends system wait mode.

1.4.2.6

Run Mode

Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save

power.

1.4.3

Freeze Mode

The enhanced capture timer, pulse width modulator, analog-to-digital converters, and the periodic interrupt

timer provide a software programmable option to freeze the module status when the background debug

module is active. This is useful when debugging application software. For detailed description of the

behavior of the ATD0, ATD1, ECT, PWM, and PIT when the background debug module is active consult

the corresponding Block Guides.

1.4.4

System States

To facilitate system integrity the MCU can run in Supervisor state or User state. The System States strategy

is implemented by additional features on the S12X CPU and a Memory Protection Unit. This is designed

to support restricted access for code modules executed by kernels or operating systems supporting access

control to system resources.

The current system state is indicated by the U bit in the CPU condition code register. In User state certain

CPU instructions are restricted. See the CPU reference guide for details of the U bit and of those

instructions affected by User state.

In the case that software task accesses resources outside those deﬁned for it in the MPU a non-maskable

interrupt is generated.

1.4.4.1

Supervisor State

This state is intended for conﬁguring the MPU for different tasks that are then executed in User state,

returning to Supervisor state on completion of each task. This is the default ’state’ following reset and can

be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the

P9S12XEP100J1VVLR Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

P9S12XEP100J1VVLR Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL