 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320DM647 Datasheet(PDF) 164 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM647 Datasheet(HTML) 164 Page - Texas Instruments |
|
|
164 / 181 page  TMS320DM647 TMS320DM648 SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009 www.ti.com Table 6-81. Ethernet Subsystem Timing Requirements (continued) PARAMETER(1) MIN NOM MAX UNITS t02 REFCLKP/N duty cycle 40 60 % t03 REFCLKP/N rise/fall 700 ps t04 PLL Clock Period, x n Mode t01 / n ns t05 PLL power up 1 + 200 * C ms REFCLKP/N Jitter and PLL Loop Bandwidth Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance. A good quality, low jitter reference clock is necessary to achieve compliance with most if not all physical layer standards (see Table 6-82). Table 6-82. REFCLKP/N Jitter Requirements for Standards Compliance Standard Line Rate (Gbps) Total REFCLKP/N Jitter (within PLL bandwidth) Gigabit Ethernet 1.25 50 ps pk-pk 164 Peripheral Information and Electrical Specifications Copyright © 2010–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
