6TPE100MPB2 datasheet(12/22 Pages) NSC

12 / 22 page

Estimate Power Dissipation And

Board Thermal Requirements

Use the current derating curves in the typical performance

characteristics section to obtain an estimate of power loss

IC_LOSS). For the design case of VIN = 5V, VOUT = 2.5V,

OUT = 3A, TA(MAX) = 85°C , and TJ(MAX) = 125°C, the device

must see a thermal resistance from case to ambient (

CA) of

less than:

Given the typical thermal resistance from junction to case

(

JC) to be 1.9°C/W (typ.). Continuously operating at a TJ

greater than 125°C will have a shorten life span.

To reach

CA = 69.5°C/W, the PCB is required to dissipate

heat effectively. With no airflow and no external heat, a good

estimate of the required board area covered by 1oz. copper

on both the top and bottom metal layers is:

As a result, approximately 7.2 square cm of 1oz. copper on

top and bottom layers is required for the PCB design.

The PCB copper heat sink must be connected to the exposed

pad (EP). Approximately thirty six, 10mils (254

μm) thermal

vias spaced 59mils (1.5 mm) apart must connect the top cop-

per to the bottom copper. For an extended discussion and

formulations of thermal rules of thumb, refer to AN-2020. For

an example of a high thermal performance PCB layout with

JA of 20°C/W, refer to the evaluation board application note

AN-2022 and for results of a study of the effects of the PCB

designs, refer to AN-2026.

PC Board Layout Guidelines

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce and resistive voltage drop in the traces. These

can send erroneous signals to the DC-DC converter resulting

in poor regulation or instability. Good layout can be imple-

mented by following a few simple design rules.

301118b5

FIGURE 1. High Current Loops

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize

the high di/dt current paths. The high current that does not

overlap contains high di/dt, see Figure 1. Therefore physically

place input capacitor (C

in1) as close as possible to the

LMZ10503 VIN pin and GND exposed pad to avoid observ-

able high frequency noise on the output pin. This will minimize

the high di/dt area and reduce radiated EMI. Additionally,

grounding for both the input and output capacitor should con-

sist of a localized top side plane that connects to the GND

exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and en-

able components should be routed only to the GND pin of the

device. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly placed,

poor grounding can result in degraded load regulation or er-

ratic output voltage ripple behavior. Provide the single point

ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R

fbt and Rfbb, and the compensation

components, R

comp and Ccomp, should be located close to the

FB pin. Since the FB node is high impedance, keep the copper

area as small as possible. This is most important as relatively

high value resistors are used to set the output voltage.

4. Make input and output bus connections as wide as

possible.

This reduces any voltage drops on the input or output of the

converter and maximizes efficiency. To optimize voltage ac-

curacy at the load, ensure that a separate feedback voltage

sense trace is made at the load. Doing so will correct for volt-

age drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad

to the ground plane on the bottom PCB layer. If the PCB has

multiple copper layers, thermal vias can also be employed to

make connection to inner layer heat-spreading ground

planes. For best results use a 6 x 6 via array with minimum

via diameter of 10mils (254

μm) thermal vias spaced 59mils

(1.5 mm). Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

6TPE100MPB2 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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