TPS23754

TPS23754-1

TPS23756

SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DUTY

POE UVLO

CONVERTER UVLO

STATUS

FEATURE

PACKAGE

MARKING

CYCLE

ON / HYST.

ON / HYST.

TPS23754PWP

Active

0–78%

35/4.5

15 / 6.5

PPD

TSSOP-20

TPS23754

PowerPAD™

TPS23754PWP-1

Active

0–78%

35/4.5

15 / 6.5

–

TSSOP-20

23754-1

PowerPAD™

TPS23756PWP

Active

0–78%

35/4.5

9 / 3.5

PPD

TSSOP-20

TPS23756

PowerPAD™

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1) (2)

VALUE

UNIT

–0.3 to 100

V

-0.3 to 6.5

V

–0.3 to 6.5

V

Input voltage range CS to [ARTN,COM]

V

Input voltage range [ARTN, COM] to RTN

–2 to 2

V

–0.3 to 19

V

V

Sinking current RTN

Internally limited

mA

Internally limited

mA

Average Sourcing or sinking current, GATE, GAT2

25

mArms

ESD rating, HBM

2

kV

ESD rating, CDM

500

V

8 / 15

kV

–40 to Internally limited

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

ARTN and COM must be tied to RTN.

(3)

(4)

Do not apply voltage to these pins

(5)

ESD per EN61000-4-2. A power supply containing the TPS23754 was subjected to the highest test levels in the standard. See the ESD

section.

2

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