TS12A4516DBVR datasheet(7/14 Pages) TI

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APPLICATION INFORMATION

Power-Supply Considerations

Logic-Level Thresholds

Test Circuits/Timing Diagrams

orNC

TS12A4516

,, TS12A4517

www.ti.com ................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009

The TS12A4516 and TS12A4517 operate with power-supply voltages from ±1 V to ±6 V [(2 V < (V+ – V–) < 12 V],

but are tested and specified at ±5V, ±3.3V, and ±1.8V supplies. The pin-compatible TS12A4514 and TS12A4515

are recommended for use when only a single supply is desirable.

The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they have

only two supply pins: V+ and V–. V+ and V– drive the internal CMOS switches and set their analog voltage limits.

Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V+ and V–.

One of these diodes conducts if any analog signal exceeds V+ or V–.

Virtually all the analog leakage current comes from the ESD diodes to V+ or V–. Although the ESD diodes on a

given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is

biased by either V+ or V– and the analog signal. This means their leakages will vary as the signal varies. The

difference in the two diode leakages to the V+ and V– pins constitutes the analog-signal-path leakage current. All

analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.

This is why both sides of a given switch can show leakage currents of the same or opposite polarity.

V+ and V– also power the internal logic and logic-level translators. The logic-level translators convert the logic

levels to switched V+ and V– signals to drive the analog signal gates.

Since these parts have no ground pin, the logic-level threshold is referenced to V+. The threshold limits are V+

–1.5 V and V+ –3.5 V for V+ levels between 6 V and 3 V. When V+ = 2 V, the logic threshold is approximately 0.6

CAUTION:

Do not connect the TS12A4516/TS12A4517 V+ to 3 V and then connect the

logic-level pins to logic-level signals that operate from 5-V supply. TTL levels

can exceed 3 V and violate the absolute maximum ratings, damaging the part

and/or external circuits.

Figure 1. Charge Injection

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