PACVGA201

Rev. 3 | Page 3 of 8 | www.onsemi.com

Ordering Information

PART NUMBERING INFORMATION

Pins

Package

Ordering Part Number

1

Part Marking

16

QSOP

PACVGA201QR

PACVGA 201QR

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

PIN DESCRIPTIONS

Pins(s)

NAME

DESCRIPTION

1

V

CC3

V

ESD protection circuits.

2

V

CC1

V

protection circuits.

3

VIDEO_1

Video signal ESD protection channel. This pin is typically tied one of the video lines between

the VGA controller device and the video connector.

4

VIDEO_2

Video signal ESD protection channel. This pin is typically tied one of the video lines between

the VGA controller device and the video connector.

5

VIDEO_3

Video signal ESD protection channel. This pin is typically tied one of the video lines between

the VGA controller device and the video connector.

6

GND

Ground reference supply pin.

7

PWR_UP

Enables the sync buffers when high. When PWR_UP is low the sync outputs are forced low

and the inputs can be floated.

8

V

CC2

V

protection circuits. Internally, V

connected to a supply voltage.

9

DDC_OUT1

DDC_OUT1 ESD protection channel.

10

DDC_OUT2

DDC_OUT2 ESD protection channel

11

SYNC_IN1

Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.

12

SYNC_OUT1

Sync signal buffer output. Connects to the video connector side of one of the sync lines.

13

SYNC_IN2

Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.

14

SYNC_OUT2

Sync signal buffer output. Connects to the video connector side of one of the sync lines.

15

SD1

ESD protection channel input.

16

SD2

ESD protection channel input.