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MC68HC705P9CS Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 160 page ![]() Resets and Interrupts Technical Data MC68HC705P9 — Rev. 4.0 66 Resets and Interrupts MOTOROLA 5.2 Resets A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. The following sources can generate resets: • Power-on reset (POR) circuit • RESET pin • COP watchdog Figure 5-1. Reset Sources 5.2.1 Power-On Reset A positive transition on the VDD pin generates a power-on reset. NOTE: The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. A 4064 t CYC (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of 4064 t CYC, the MCU remains in the reset condition until the signal on the RESET pin goes to logic one. DQ CK S RESET LATCH POWER-ON RESET COP WATCHDOG (PROGRAMMABLE OPTION) INTERNAL CLOCK RST TO CPU AND RESET V DD SUBSYSTEMS Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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