LMZ14202 datasheet(13/18 Pages) NSC

13 / 18 page

Given the typical thermal resistance from junction to case to

be 1.9 °C/W. Use the 85°C power dissipation curves in the

Typical Performance Characteristics section to estimate the

IC-LOSS for the application being designed. In this application

it is 1.5W.

CA = (125 — 85) / 1.5W — 1.9) = 24.8

To reach

CA = 24.8, the PCB is required to dissipate heat

effectively. With no airflow and no external heat, a good esti-

mate of the required board area covered by 1 oz. copper on

both the top and bottom metal layers is:

Board Area_cm2 = 500°C x cm2/W /

JC (19)

As a result, approximately 20.2 square cm of 1 oz copper on

top and bottom layers is required for the PCB design. The

PCB copper heat sink must be connected to the exposed pad.

Approximately thirty six, 10mils (254

μm) thermal vias spaced

59mils (1.5 mm) apart must connect the top copper to the

bottom copper. For an example of a high thermal performance

PCB layout, refer to the Evaluation Board application note

AN-2024.

PC BOARD LAYOUT GUIDELINES

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce and resistive voltage drop in the traces. These

can send erroneous signals to the DC-DC converter resulting

in poor regulation or instability. Good layout can be imple-

mented by following a few simple design rules.

30114511

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize

the high di/dt paths during PC board layout. The high current

loops that do not overlap have high di/dt content that will

cause observable high frequency noise on the output pin if

the input capacitor (Cin1) is placed at a distance away from

the LMZ14202. Therefore place C

IN1 as close as possible to

the LMZ14202 VIN and GND exposed pad. This will minimize

the high di/dt area and reduce radiated EMI. Additionally,

grounding for both the input and output capacitor should con-

sist of a localized top side plane that connects to the GND

exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and en-

able components should be routed to the GND pin of the

device. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly handled,

poor grounding can result in degraded load regulation or er-

ratic output voltage ripple behavior. Provide the single point

ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R

FBT and RFBB, and the feed forward

capacitor C

FF, should be located close to the FB pin. Since

the FB node is high impedance, maintain the copper area as

small as possible. The trace are from R

FBT, RFBB, and CFF

should be routed away from the body of the LMZ14202 to

minimize noise.

4. Make input and output bus connections as wide as

possible.

This reduces any voltage drops on the input or output of the

converter and maximizes efficiency. To optimize voltage ac-

curacy at the load, ensure that a separate feedback voltage

sense trace is made to the load. Doing so will correct for volt-

age drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad

to the ground plane on the bottom PCB layer. If the PCB has

a plurality of copper layers, these thermal vias can also be

employed to make connection to inner layer heat-spreading

ground planes. For best results use a 6 x 6 via array with

minimum via diameter of 10mils (254

μm) thermal vias spaced

59mils (1.5 mm). Ensure enough copper area is used for heat-

sinking to keep the junction temperature below 125°C.

LMZ14202 Datasheet(PDF) 13 Page - National Semiconductor (TI)

LMZ14202 Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL