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2-112
RF2132
Rev B9 010417
2
Application Schematic
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BIAS
1.8 nH
100 pF
18 k
Ω
100 pF
RF IN
V
PC
1nF
1nF
100 pF
6.8 nH
3pF
V
CC
12 pF
3.3 nH
4.3 pF
100 pF
RF OUT
Vcc = 4.8 V
Vpc = 4.0 V
BIAS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
1.8 nH
C6
100 pF
R1
18 k
Ω
C14
100 pF
C13
1nF
C12
3.3
µF
P1-3
C8
33 pF
J1
L3
3.3 nH
C11
4.3 pF
C9
100 pF
J2
C7
3pF
L2
6.8 nH
C4
1nF
C1
100 nF
C2
11
µF
C3
1
µF
C10
12 pF
P1-1
C5
100 pF
RF IN
RF OUT
P1-1
P1-3
P1
PC
GND
VCC
1
2
3
Vcc = 4.8 V
Vpc = 4.0 V
Power supply filtering/bypassing for V
cc
Power supply filtering/bypassing for V
PC
Adds bias to the first
amplifier stage for
improved linearity
Bias inductor for the
amplifier output stage
Harmonic trap: C7 series resonates with
internal bondwires of pins 14 and 15 at
2f
0 to effectively short out 2nd harmonic
for optimum gain and efficiency
Matching network for
optimum load impedance
Interstage tuning (L1) for
centering output frequency
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