Preliminary
2-199
RF5176
Rev A0 010910
2
Pin
Function
Description
Interface Schematic
1VREG1
Bias control for the first stage. Needs to be divided down from its nomi-
nal value of 2.5V using a resistive divider network of 240k
Ω and
360k
Ω.V
REG1 and VREG2 maybe adjusted tominimizeidlecurrent for
a given output power. Alternative VREG voltages can be used as
defined on the application schematic.
2
VCC BIAS
Supply for bias circuits.
3VREG2
Bias control for the second stage. Needs to be divided down from its
nominal value of 2.5V using a resistive divider network of 240k
Ω and
240k
Ω.Alternative V
REG voltages can be used as defined on the appli-
cation schematic.
4
VS2
Second stage bias circuit source. For best linearity, decouple with
bypassing capacitors of 15pF and 100nF.
5BIAS GND
Connect to ground plane via a 15nH inductor. DC return for the second
stage bias circuit.
6NC
Not currently used.
7NC
Not currently used.
8RF OUT
RF output and power supply for the final stage. This is the unmatched
collector of the final stage. It requires an output matching network,
including a DC blocking capacitor.
9RF OUT
Same as pin 8.
10
RF OUT
Same as pin 8.
11
NC
Not currently used.
12
VCC1
Power supply for the first stage and interstage match. Requires a shunt
capacitor of 12pF close to the pin for optimum match.
13
VCC1
Same as pin 12.
14
NC
Not currently used.
15
NC
Not currently used.
16
RF IN
RF input. Requires a blocking capacitor and shunt inductor to provide
2:1 VSWR.
17
NC
Not currently used.
18
Q1B
Base bias for first stage. For best linearity, decouple with 15pF and
100nF capacitors.
19
NC
Not currently used.
20
NC
Not currently used.
Pkg
Base
GND
Ground connection. The backside of the package should be soldered
to a top side ground pad which is connected to the ground plane with
multiple vias. The pad should have a short thermal path to the ground
plane.
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