175

Audio ICs

BU1920 / BU1920F / BU1920FS

FOutput data timing

The clock (RCLK) frequency is 1187.5Hz. Depending on

the state of the internal PLL clock, the data (RDATA) is

replaced in synchronous with either the rising or falling

edge of the clock. To read the data, you may

choose either the rising or falling edge of the clock as the

reference. The data is valid for 416.7

µs, after the refer-

ence clock edge.

QUAL pin operation: Indicates the quality of the demodu-

lated data.

(1)

Good data

: HI

(2)

Poor data

: LO

ARI pin operation: ARI / RDS discrimination.

(1)

ARI

: LO

(2)

RDS + ARI

: LO

(3)

RDS

: HI

(4)

No signal

: unstable

FElectrical characteristics curve