5

Memory ICs

BU9877FV

Parameter

Symbol

Typ.

Max.

Min.

Unit

Data clock HIGH time

t HIGH

——

4.0

µs

t SU: STA

——

Start condition setup time

4.7

µs

t PD

—

3.5

—

Output data delay time

µs

t DH

——

0.3

Output data hold time

µs

t SU:STO

——

4.7

Stop condition setup time

µs

t BUF

——

4.7

Bus release time prior to start of transfer

µs

t I

—

0.1

Effective noise elimination interval (SCL, SDA pins)

—

µs

t HD: STA

——

Start condition hold time

4.0

µs

t F

—

0.3

SDA / SCL fall time

—

µs

t R

—

SDA / SCL rise time

1.0

—

µs

t LOW

Data clock LOW time

—

—

4.7

µs

t HD: DAT

——

Input data hold time

0

ns

t SU: DAT

——

Input data setup time

250

ns

t WR1

—

10

—

ms

t WR2

—

15

—

ms

Internal write cycle time

(3) Start condition (start bit recognition)

Before executing the various commands, a start condi-

tion (start bit) must be input. This is recognized when

SCL is HIGH and SDA falls from HIGH to LOW.

If a start condition is not input, no commands will be

received.

(4) Stop condition (stop bit recognition)

To terminate the various commands, a stop condition

(stop bit) must be input. This is recognized when SCL

is HIGH and SDA rises from LOW to HIGH.

(5) Precautions concerning the write command

With the write command, internal writing is initiated by

inputting the stop bit after the data has been input.

(6) Device addressing (specifying the slave address)

The master address should be output first, followed by

the start condition, and then the slave address. The

first four bits of the slave address are used to recog-

nize the device type. The device code for this IC is

fixed at "1010". When accessing the write protect regis-

ter, a device code of "0110" is used.

The next three bits of the slave address (A2, A1, A0)

are used to select the device, and the IC begins to

function only if the data input for A2 to A0 matches the

states of input pins A2 to A0. Consequently, up to eight

of these ICs may be connected on the same bus,

depending on the combination of A2 to A0.

The last bit of the slave address (R / W) is used to

specify either writing or reading, and is as shown

below.

R / W set to 0: Writing or Random Read

R / W set to 1: Reading

Device type

Device address

Access to write protect register

Access to memory

A2

A2

A0

A0

A1

A1

0110

1010

R / W

W