S6B0708

64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX

LCD

10

FUNCTIONAL DESCRIPTION

CHIP SELECT INPUT

The S6B0708 has two chip select pins, CS1B and CS2B. It can interface with a microprocessor when these pins

(CS1B or CS2B) are low. When both of these pins are set to high, DB0 to DB7 are at high impedance and RS,

RW, and E inputs are disabled. CS1B pin controls the display status of S1 to S64, and CS2B does that of S65 to

S128. When CS1B and CS2B are low at the same time, it is impossible to execute read operation. Therefore

one of CS1B or CS2B should be set to low ((CS1B = H & CS2B = L) or (CS1B = L & CS2B = H)) in read

operation. The RESETB signal is entered independent of the status of chip select.

Table 2. Relationship Between Chip Select Pins and Read/Write Operation

CS1B

CS2B

Read Operation

W rite Operation

CS1

CS2

CS1

CS2

H

H

X

X

X

X

L

H

O

X

O

X

H

L

X

O

X

O

L

L

-

-

O

O

( -:

Not recommended,

MICROPROCESSOR INTERFACE

S6B0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the S6B0708

through the 8-bit I/O buffer (DB0 to DB7). RS, RW and E identify the type of parallel data transfer to be made as

shown below in Table 3.

Table 3. Microprocessor Interface

RS

RW

Description

H

H

Read display data

H

L

Write display data

L

H

Status read

L

L

Write to internal register (instruction)