1

FEATURES

PINOUT ASSIGNMENT

1

8

2

7

3

6

4

5

+

+

Q

0

Q

0

Q

1

Q

1

V

CC

D

D

V

EE

DESCRIPTION

SN65LVEP11

2.5 V/3.3 V PECL/ECL 1:2 Fanout Buffer

• 1:2 PECL/ECL Fanout Buffer

• Operating Range

–

–

–3.8 V

• Open Input Default State

• Support for Clock Frequencies > 3.0 GHz

• 240 ps Typical Propagation Delay

• Deterministic Output Value for Open Input

Conditions

• Q Output Will Default Low When Input Open or

• Built-in Temperature Compensation

Table 1. PIN DESCRIPTION

• Drop in Compatible to MC10LVEP11,

PIN

FUNCTION

MC100LVEP11

D, D

PECL/ECL data inputs

• LVDS Input Compatible

PECL/ECL outputs

Positive supply

Negative supply

The SN65LVEP11 is a differential 1:2 PECL/ECL

fanout

buffer.

The

device

includes

circuitry

to

maintain known logic levels when the inputs are in an

open condition. Single-ended clock input operation is

NECL

mode.

The

device

is

housed

in

an

industry-standard

SOIC-8

package

and

is

also

available in TSSOP-8 package option.

PART NUMBER

PART MARKING

PACKAGE

LEAD FINISH

SN65LVEP11D

SN65LVEP11

SOIC

NiPdAu

SN65LVEP11DGK

SN65LVEP11

SOIC-TSSOP

NiPdAu

(1)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.