methodology for the synthesis of custom analog circuits”, Proc.

ICCAD 2001, pp 350-357. Shown in figure 3.

Technology: IBM 0.5um BSIM3v3 models, obtained from

http://www.mosis.org/test

METRIC

SPECIFICATION

RESULT

Gain

≥ 68 dB

72.6 dB

Unity gain BW

≥ 255 MHz

697 MHz

Phase margin

≥ 52 degrees

56 degrees

CMRR

≥ 55 dB

56.2 dB

PSRR (Vdd)

≥ 80 dB

86.5 dB

Slew rate

≥ 250 V/us

403 V/us

Propagation delay

≤ 2 ns

1.13 ns

Area

≤ 24000 sq. micron

6000 sq. micron

Ultra wide-band OpAmp

Source: Advanced VLSI Design Lab, Indian Institute of Technol-

ogy, Kharagpur, shown in figure 4.

Technology: TSMC 0.18um BSIM3v3 models, obtained from

http://www.mosis.org/test

METRIC

SPECIFICATION

RESULT

Gain

≥ 60 dB

67.5 dB

Unity gain BW

≥ 2 GHz

2.18 GHz

Phase margin

≥ 50 degrees

55 degrees

ICMR

-

0.4 - 1.5 V

CMRR

-

86 dB

PSRR (Vdd)

-

83 dB

Settling time

-

3 ns

Static power

≤ 50 mW

46 mW

Table 2: Specification and optimization for ultra wide band

OpAmp

Missing entries in the specification column denote metrics which

were not part of the optimization objectives, but measured post

optimization.

High gain OpAmp

Source: Advanced VLSI Design Lab, Indian Institute of Technol-

ogy, Kharagpur, shown in figure 5.

Technology: TSMC 0.18um BSIM3v3 models, obtained from

http://www.mosis.org/test

Table 1: Specification and optimization for two stage OpAmp

- +

+ -

- +

+ -

node1

node2

node0

node3

node4

node5

node6

bias

node7

VinN

VinP

Vout

Vdd

gnd

M0

M10

M8

M7

M5

M6

M3

M4

M1

M2

Rz

- +

+ -

- +

+ -

node1

node2

node0

node3

node4

node5

node6

bias

node7

VinN

VinP

Vout

Vdd

gnd

nbiias

M0

M9

M10

M8

M7

M5

M6

M3

M4

M1

M2

Rz

Cc

Figure 5: High gain OpAmp schematic, with gain-booster stage

shown as a block.

AnXplorer: EDA Tool for Schematic Level Optimization of Analog & RF Circuits

Figure 3: Two stage OpAmp schematic

Figure 4: Ultra wide-band OpAmp schematic