ADP3654 datasheet(3/12 Pages) AD

3 / 12 page

ADP3654

Rev. 0 | Page 3 of 12

SPECIFICATIONS

VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SUPPLY

Supply Voltage Range

VDD

4.5

Supply Current

IDD

No switching

1.2

UVLO

Turn-On Threshold Voltage

VUVLO_ON

VDD rising, TJ = 25°C, see Figure 3

3.8

4.2

4.5

Turn-Off Threshold Voltage

VUVLO_OFF

VDD falling, TJ = 25°C, see Figure 3

3.5

3.9

4.3

Hysteresis

0.3

DIGITAL INPUTS (INA, INB)

Input Voltage High

VIH

See Figure 2

2.0

Input Voltage Low

VIL

See Figure 2

0.8

Input Current

IIN

0 V < VIN < VDD

−20

+20

μA

Internal Pull-Up/Pull-Down Current

μA

OUTPUTS (OUTA, OUTB)

Output Resistance, Unbiased

VDD = PGND

kΩ

Peak Source Current

See Figure 14

Peak Sink Current

See Figure 14

−4

SWITCHING TIME

OUTA and OUTB Rise Time

tRISE

CLOAD = 2.2 nF, see Figure 2

OUTA and OUTB Fall Time

tFALL

CLOAD = 2.2 nF, see Figure 2

OUTA and OUTB Rising Propagation Delay

tD1

CLOAD = 2.2 nF, see Figure 2

OUTA and OUTB Falling Propagation Delay

tD2

CLOAD = 2.2 nF, see Figure 2

Delay Matching Between Channels

1 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.

TIMING DIAGRAMS

INA,

INB

OUTA,

OUTB

tD1

tRISE

10%

90%

10%

90%

VIH

VIL

tD2

tFALL

Figure 2. Output Timing Diagram

NORMAL OPERATION

UVLO MODE

OUTPUTS DISABLED

VDD

VUVLO_ON

VUVLO_OFF

UVLO MODE

OUTPUTS DISABLED

Figure 3. UVLO Function

ADP3654 Datasheet(PDF) 3 Page - Analog Devices

ADP3654 Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL