PT6520

V1.9

17

July 2010

READ/WRITE TIMING FOR THE 68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

Min.

Typ.

Max

Unit

System cycle time

A0, CS, R/W

tCYC6

VSS=-5V

1000

-

-

ns

VSS=-3V

2000

-

-

ns

Address set-up time

tAW6

VSS=-5V

20

-

-

ns

VSS=-3V

40

-

-

ns

Address hold time

tAH6

VSS=-5V

10

-

-

ns

VSS=-3V

30

-

-

ns

Control pulse width

D0~D7

tDS6

VSS=-5V

80

-

-

ns

VSS=-3V

160

-

-

ns

Data set-up time

tDH6

VSS=-5V

10

-

-

ns

VSS=-3V

20

-

-

ns

Data hold time

tOH6

CL=100pF VSS=-5V

10

-

60

ns

CL=100pF

VSS=-3V

20

-

120

ns

RD access time

tACC6

CL=100pF VSS=-5V

-

-

200

ns

CL=100pF

VSS=-3V

-

-

400

ns

Enable disable time

READ

E

tew

VSS=-5V

250

-

-

ns

VSS=-3V

400

-

-

ns

WRITE

VSS=-5V

150

-

-

ns

VSS=-3V

250

-

-

ns

Note: tCYC6 indicates the cycle during which CS/E are high; it does not indicate are cycle of the E signal.

CONTROL TIMING FOR 80-PORT/68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

Min.

Typ.

Max

Unit

Reset time

RES

tR

VSS=-5V

1

-

750

μs

VSS=-3V

1.5

-

1000

μs

Reset time

(68-Port)

RES

tR1

VSS=-5V

1

-

-

μs

VSS=-3V

1.5

-

-

μs

Reset time

(80-Port)

RES

tR2

VSS=-5V

1

-

-

μs

VSS=-3V

1.5

-

-

μs

Notes:

1. The input timing of the FR delay time is determined by the PT6520 (Slave)

2. The output timing of the FR delay time is determined by the PT6520 (Master)