117 datasheet(112/114 Pages) RENESAS

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Revision History

R32C/117 Group Datasheet

Rev.

Date

Description

Page

Summary

1.00

Nov 19, 2009

—

Initial release

1.01

Mar 11, 2010

—

Second edition released

—

• Added “128 KB/20KB” and “256KB/20KB” for ROM/RAM capacity

1.10

Jun 23, 2010

—

Third edition released

This manual in general

—

• Applied new Renesas templates and formats to the manual

• Changed company name to “Renesas Electronics Corporation” and

changed related descriptions due to business merger of Renesas

Technology Corporation and NEC Electronics Corporation (under

Chapters 1 and 5)

• Added specifications of 64 MHz version

Chapter 1. Overview

3, 5

• Deleted Note 1 from Tables 1.2 and 1.4

• Completed “under development” phase of part number R5F6417BDFB

in Table 1.5

• Deleted Note 4 from Figure 1.2

• Modified expression “fC” in Table 1.16 to “low speed clocks”

Chapter 4. SFRs

36, 39

• Changed register name “Group i Timer Measurement Prescaler

Prescaler Register”

• Modified expression “XY Control Register” in Table 4.11 to “X-Y

Control Register”

• Changed register name “UART2 Transmission/Receive Mode

Changed hexadecimal format of reset values for registers TABSR,

ONSF, and TRGSR to binary

• Changed register name “External Interrupt Source Select Register i” in

Table 4.24

to “External Interrupt Request Source Select Register i”

• Modified register names “CAN0 Reception Error Count Register” and

“CAN0 Transmission Error Count Register” in Table 4.39 to “CAN0

Receive Error Count Register” and “CAN0 Transmit Error Count

Chapter 5. Electrical Characteristics

• Changed expressions “

CS0” and “A23 to A0, BC3 to BC0” in Figure

5.5

to “Chip select” and “Address”, respectively

Appendix 1. Package Dimensions

111

• Added a seating plane to the drawing of package dimension

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