LPC1102 datasheet(2/38 Pages) NXP

2 / 38 page

LPC1102

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Objective data sheet

Rev. 00 — 23 June 2010

2 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

One SPI controller with SSP features and with FIFO and multi-protocol capabilities

(see Section 7.16).

Clock generation:

12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used

as a system clock.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from an external clock or the internal RC

oscillator.

Clock output function with divider that can reflect the external clock, IRC clock,

CPU clock, and the Watchdog clock.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep and Deep-sleep modes.

Two reduced power modes: Sleep and Deep-sleep modes.

Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

six of the functional pins.

Power-On Reset (POR).

Brownout detect with four separate thresholds for interrupt and forced reset.

Unique device serial number for identification.

Single 3.3 V power supply (1.8 V to 3.6 V).

Available as WLCSP16 package.

Applications

Ordering information

4.1 Ordering options

Mobile devices

8-/16-bit applications

Consumer peripherals

Portable devices

Lighting

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1102

WLCSP16

wafer level chip-size package; 16 bumps; 2.17

× 2.32 × 0.6 mm

Table 2.

Ordering options

Type number

Flash

Total

SRAM

UART

RS-485

SPI

ADC

channels

Package

LPC1102

32 kB

8 kB

WLCSP16

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