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AT91SAM9G45 Datasheet(PDF) 49 Page - ATMEL Corporation |
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AT91SAM9G45 Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 56 page ![]() 49 6438ES–ATARM–21-Jun-10 AT91SAM9G45 • Embedded 4-KByte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • Up to 2 or 3 banks for isochronous and bulk endpoints • Seven endpoints: – Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, High Bandwidth, DMA – Endpoint 3 & 4: 1024 bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 banks mode, High Bandwidth, DMA 10.11 LCD Controller (LCDC) • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported. • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048 x 2048 10.12 Touch Screen Analog-to-Digital Converter (TSADC) • 8-channel ADC • Support 4-wire resistive Touch Screen • 10-bit 384 Ksamples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources – Hardware or software trigger – External trigger pin • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 10.13 Ethernet 10/100 MAC (EMAC) • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations |
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