IRMCK371

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© 2007 International Rectifier

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TABLE OF FIGURES

Figure 1. Typical Application Block Diagram Using IRMCK371.....................................................5

Figure 2. IRMCK371 Internal Block Diagram.................................................................................6

Figure 3. IRMCK371 Pin Configuration..........................................................................................8

Figure 4. Input/Output of IRMCK371 .............................................................................................9

Figure 5. Application Connection of IRMCK371 ..........................................................................12

Figure 6. Clock Frequency vs. Power Consumption....................................................................13

Figure 7 Crystal oscillator circuit..................................................................................................16

Figure 8 Voltage droop of sample and hold.................................................................................17

Figure 9 SYNC to SVPWM and A/D Conversion AC Timing .......................................................18

Figure 10 GATEKILL to SVPWM AC Timing ...............................................................................19

Figure 11 Interrupt AC Timing .....................................................................................................19

Figure 12 I2C AC Timing ..............................................................................................................20

Figure 13 SPI write AC Timing.....................................................................................................21

Figure 14 SPI read AC Timing.....................................................................................................22

Figure 15 UART AC Timing .........................................................................................................23

Figure 16 CAPTURE Input AC Timing.........................................................................................24

Figure 17 JTAG AC Timing..........................................................................................................25

Figure 18 OTP Programming Timing ...........................................................................................26

Figure 19 All digital I/O except motor PWM output.........................................................................27

Figure 20 RESET, GATEKILL I/O ..................................................................................................27

Figure 21 Analog input ...................................................................................................................28

Figure 22 Analog operational amplifier output and AREF I/O structure.......................................28

Figure 23 VPP programming pin I/O structure

..........................................................................28

Figure 24 VSS, AVSS and PLLVSS pin structure ..........................................................................29

Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure ...........................................................29

Figure 26 XTAL0/XTAL1 pins structure .......................................................................................29