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80C86 Datasheet(PDF) 22 Page - Intersil Corporation |
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80C86 Datasheet(HTML) 22 Page - Intersil Corporation |
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22 / 37 page ![]() 22 FN2957.3 January 9, 2009 AC Electrical Specifications VCC = 5.0V ±10%TA = 0°C to +70°C (C80C86, C80C86-2) VCC = 5.0V ±10%;TA = -55°C to +125°C (M80C86) VCC = 5.0V ±5%;TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TIMING REQUIREMENTS TEST CONDITIONS 80C86 80C86-2 UNITS SYMBOL PARAMETER MIN MAX MIN MAX MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) Timing Requirements (1) TCLCL CLK Cycle Period 200 125 ns (2) TCLCH CLK Low Time 118 68 ns (3) TCHCL CLK High Time 69 44 ns (4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V 10 10 ns (5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V 10 10 ns (6) TDVCL Data in Setup Time 30 20 ns (7) TCLDX1 Data In Hold Time 10 10 ns (8) TR1VCL RDY Setup Time into 82C84A (Notes 11, 12) 35 35 ns (9) TCLR1X RDY Hold Time into 82C84A (Notes 11, 12) 00 ns (10) TRYHCH READY Setup Time into 80C86 118 68 ns (11) TCHRYX READY Hold Time into 80C86 30 20 ns (12) TRYLCL READY Inactive to CLK (Note 13) -8 -8 ns (13) TlNVCH Setup Time for Recognition (lNTR, NMl, TEST) (Note 12) 30 15 ns (14) TGVCH RQ/GT Setup Time 30 15 ns (15) TCHGX RQ Hold Time into 80C86 (Note 14) 40 TCHCL + 10 30 TCHCL + 10 ns (16) TILlH Input Rise Time (Except CLK) From 0.8V to 2.0V 15 15 ns (17) TIHIL Input Fall Time (Except CLK) From 2.0V to 0.8V 15 15 ns Timing Responses (18) TCLML Command Active Delay (Note 11) CL = 100pF for All 80C86 Outputs (In Addition to 80C86 Self Load) 5 35535 ns (19) TCLMH Command Inactive (Note 11) CL = 100pF for All 80C86 Outputs (In Addition to 80C86 Self Load) 5 35535 ns (20) TRYHSH READY Active to Status Passive (Notes 13, 15) CL = 100pF for All 80C86 Outputs (In Addition to 80C86 Self Load) 110 65 ns (21) TCHSV Status Active Delay CL = 100pF for All 80C86 Outputs (In Addition to 80C86 Self Load) 10 110 10 60 ns 80C86 |
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