data has to be followed by an acknowledge bit. The acknowl-

edge related clock pulse is generated by the master. The

master releases the SDA line (HIGH) during the acknowledge

clock pulse. The LM2759 pulls down the SDA line during the

9th clock pulse, signifying an acknowledge. The LM2759 gen-

erates an acknowledge after each byte is received.

dress. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). The LM2759 address

is 53h. For the eighth bit, a “0” indicates a WRITE and a “1”

indicates a READ. The second byte selects the register to

which the data will be written. The third byte contains data to

write to the selected register.

30069312

FIGURE 3. Write Cycle

w = write (SDA = "0")

r = read (SDA = "1")

ack = acknowledge (SDA pulled down by either master or slave)

id = chip address, 53h for LM2759

The chip address for LM2759 is 1010011, or 53h.

30069309

INTERNAL REGISTERS

30069308

30069305

30069306

30069307

Register

Internal Hex

Address

Power On Value

(lowest 4 bits)

General Purpose

Register

10h

0000

Flash Current

Register

B0h

1010

Torch Current

Register

A0h

0111

Flash Timeout

Duration Register

C0h

1011

GENERAL PURPOSE REGISTER AND STROBE INHIBIT

FUNCTION

The general purpose register (x10) is used set the mode of

operation for the LM2759. The selectable operating modes

using the lower 4 bits in the general purpose register are listed

in the table below.

signals into this pin when desired. This function is implement-

ed through bit 3 of the General Purpose Register (See table

below). In the default state, input signals on the Strobe Input

are enabled. (Bit3 = “0”, inputs into the Strobe Pin are not

inhibited).

General Purpose Register (Reg x10)

Bit3

Bit2

Bit1

Bit0

Mode

X

X

X

0

Shutdown

X

0

0

1

Torch

X

X

1

1

Flash

X

1

0

1

Indicator (Lowest Torch Level)

1

X

X

X

Inhibit Inputs into the Strobe Pin

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