LM4549B datasheet(23/28 Pages) NSC

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SR2:SR0

Source for Right Channel ADC

Mono Mix

PHONE input

Default: 0000h

RECORD GAIN REGISTER (1Ch)

This register controls the input levels for both channels of the

stereo ADC. The inputs come from the Record Select Mux

and are selected via the Record Select Control register, 1Ah.

The gain of each channel can be individually programmed

from 0dB to +22.5 dB in 1.5 dB steps. Both channels can

also be muted by setting the MSB to 1.

Record Gain Register (1Ch)

Mute

Gx3:Gx0

Function

1111

22.5 dB gain

0000

0 dB gain

XXXX

*mute

Default: 8000h

GENERAL PURPOSE REGISTER (20h)

This register controls many miscellaneous functions imple-

mented on the LM4549B. The miscellaneous control bits

include POP which allows the DAC output to bypass the

National 3D Sound circuitry, 3D which enables or disables

the National 3D Sound circuitry, MIX which selects the MO-

NO_OUT source, MS which controls the Microphone Selec-

tion mux and LPBK which connects the output of the stereo

ADC to the input of the stereo DAC. LPBK provides a

mixed-mode analog and digital loopback path between ana-

log inputs and analog outputs. This is an 18 bit digital loop-

back at 48 kHz, bypassing the SRC logic, even if a sample

rate other than 48 kHz is selected.

BIT

Function

POP

PCM Out Path:

*0 = 3D allowed

1 = 3D bypassed

National 3D Sound:

*0 = off

1= on

MIX

Mono output select:

*0 = Mix

1 = Mic

Mic select:

*0 = MIC1

1 = MIC2

LPBK

ADC/DAC Loopback:

*0 = No Loopback

1 = Loopback

Default: 0000h

3D CONTROL REGISTER (22h)

This read-only (0101h) register indicates, in accordance with

the AC ’97 Rev 2.1 Specification, the fixed depth and center

characteristics of the National 3D Sound stereo enhance-

ment.

POWERDOWN CONTROL / STATUS REGISTER (26h)

This read/write register is used both to monitor subsystem

readiness and also to program the LM4549B powerdown

states. The 4 LSBs indicate status and 7 of the 8 MSBs

control powerdown.

The 4 LSBs of this register indicate the status of the 4 audio

subsections of the codec: Reference voltage, Analog mixers

and amplifiers, DAC section, ADC section. When the "Codec

Ready" indicator bit in the AC Link Input Frame (SDATA_IN:

slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97

registers are in a fully operational state and that control and

status information can be transferred. It does NOT indicate

that the codec is ready to send or receive audio PCM data or

to pass signals through the analog I/O and mixers. To deter-

mine that readiness, the Controller must check that the 4

LSBs of this register are set to “1” indicating that the appro-

priate audio subsections are ready.

The powerdown bits PR0 – PR5 control internal subsections

of the codec. They are implemented in compliance with AC

’97 Rev 2.1 to support the standard device power manage-

ment states D0 – D3 as defined in the ACPI and PCI Bus

Power Management Specification.

PR0 controls the powerdown state of the ADC and associ-

ated sampling rate conversion circuitry. PR1 controls power-

down for the DAC and the DAC sampling rate conversion

circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,

National 3D Sound, Mono Out, Line Out). PR3 powers down

REF in addition to all the same mixer circuits as PR2. PR4

powers down the AC Link digital interface – see Figure 8 for

signal powerdown timing. PR5 disables internal clocks. PR6

is not used. EAPD controls the External Amplifier Power-

Down bit.

BIT#

BIT

Function: Status

ADC

1 = ADC section ready to

transmit data

DAC

1 = DAC section ready to

accept data

ANL

1 = Analog mixers ready

REF

1 = V

REF is up to nominal level

BIT#

BIT

Function: Powerdown

PR0

1 = Powerdown ADCs and

Record Select Mux

PR1

1 = Powerdown DACs

PR2

1 = Powerdown Analog Mixer

REF still on)

PR3

1 = Powerdown Analog Mixer

REF off)

PR4

1 = Powerdown AC Link digital

interface (BIT_CLK off)

PR5

1 = Disable Internal Clock

PR6

Not Used

EAPD

External Amplifier PowerDown

*0 = Set EAPD Pin to 0 (pin 47)

Default: 000Fh If ready; otherwise 000Xh

EXTENDED AUDIO ID REGISTER (28h)

This read-only (X001h) register identifies which AC ’97 Ex-

tended Audio features are supported. The LM4549B features

VRA (Variable Rate Audio) and ID1, ID0 (Multiple Codec

LM4549B Datasheet(PDF) 23 Page - National Semiconductor (TI)

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