LM48822TL datasheet(9/22 Pages) NSC

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Application Information

I2C COMPATIBLE INTERFACE

The LM48822 is controlled through an I2C compatible serial

interface that consists of a serial data line (SDA) and a serial

clock (SCL). The clock line is uni-directional. The data line is

bi-directional (open collector). The LM48822 and the master

can communicate at clock rates up to 400kHz. Figure 2 shows

the I2C interface timing diagram. Data on the SDA line must

be stable during the HIGH period of SCL. The LM48822 is a

transmit/receive slave-only device, reliant upon the master to

generate the SCL signal. Each transmission sequence is

framed by a START condition and a STOP condition (Figure

3). Each data word, device address and data, transmitted

over the bus is 8 bits long as is always followed by an ac-

knowledge pulse (Figure 4). The LM48822 device address is

1100000.

2C BUS FORMAT

The I2C bus format is shown in Figure 4. The START signal,

the transition of SDA from HIGH to LOW while SDA is HIGH,

is generated, altering all devices on the bus that a device ad-

dress is being written to the bus.

The 7-bit device address is written to the bus, most significant

bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the

master is writing to the slave device, R/W = 1 indicates the

master wants to read data from the slave device. The

LM48822 is a WRITE-ONLY device and will not respond the

R/W = 1. The data is latched in on the rising edge of the clock.

Each address bit must be stable while SDA is HIGH. After the

last address bit is transmitted, the master device releases

SDA, during which time, an acknowledge clock pulse is gen-

erated by the slave device. If the LM48822 receives the

correct address, the device pulls the SDA line low, generating

and acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit reg-

ister data word is sent. Each data bit should be stable while

SCL is HIGH. After the 8-bit register data word is sent, the

LM48822 sends another ACK bit. Following the acknowl-

edgement of the register data word, the master issues a

STOP bit, allowing SDA to go high while SDA is high.

30061001

FIGURE 2. I2C Timing Diagram

30061002

FIGURE 3. Start and Stop Diagram

30061014

FIGURE 4. Example I2C Write Cycle

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