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FPD95220 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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FPD95220 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 2 page  PRELIMINARY September 2007 FPD95220 320-Channel LTPS Dot Inversion Driver with Programmable Partial Display General Description The FPD95220 is a 320–channel LTPS dot inversion driver with Partial Display Memory, and an 18–bit RGB video inter- face. It provides 320 output source drivers with a 1:3 glass multiplex ratio. It includes a 77,112–bit memory for partial display modes, a timing controller with glass interface level- shifters, a DC V COM driver and glass power supply circuits. The output format can be configured to drive arbitrary display resolutions up to 320 RGB columns. The on-chip Partial Display Memory is configurable in window size, location and color depth. This memory can be used to self-refresh a region of the display in a reduced power state. The FPD95220 device also includes independent RGB gam- ma curve adjustments as well as user-definable color palettes for 1–bit and 3–bit Partial Display modes. A low-speed serial interface controls display operating modes and provides access to the Partial Display Memory. This in- terface can support both 8–bit and 9–bit protocols. A standard command set is supported to set display modes and operating parameters. Customized register profiles associated with commands are loaded from an on-chip EEPROM. Registers can also be directly accessed by using the Register Access Mode. Features ■ Dot Inversion ■ Reduced audible and electrical noise for touch panel applications ■ Improved image quality ■ Supports pixel and sub-pixel inversion modes ■ Power Savings ■ Self-refreshed Partial Display Mode ■ Charge-sharing power saving functions ■ Backlight brightness PWM circuit ■ Standard Command Set ■ Registers initialized from on-chip EEPROM ■ Command-triggered profiles can change register settings for modes/gamma settings ■ Eliminates frequent host SW changes to update register settings ■ 8 user-defined display configurations ■ Programmable Settings ■ Display resolution and glass signal timing ■ Video interface timing auto-learning circuit ■ VID_XFR output reduces tearing in partial mode ■ Gamma curves and V COM adjustment ■ Partial Display ■ Adjustable memory window size and location ■ 1, 3, 12 or 18–bit color depth ■ Partial window 2x upscale with border color ■ Alpha blending, including transparent mode ■ Interfaces ■ Low-speed serial interface for commands, register access and partial memory access ■ 18–bit RGB Video interface System Diagrams 30036805 © 2007 National Semiconductor Corporation 300368 www.national.com |
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