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MAX7389 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX7389 Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 10 page ![]() Detailed Description The MAX7391 replaces ceramic resonators, crystals, and supervisory functions for microcontrollers in 3.3V and 5V applications. The MAX7391 provides a clock source, reset, and power-fail functions. The power-fail output provides early warning of power failure. The power-fail threshold is configurable to detect either an external voltage or the VCC supply voltage to the device. The clock output can be switched between normal and half-speed operation. This functionality allows the microcontroller to operate at reduced power and may be used to extend the time available to perform house- keeping tasks, such as writing data to flash, during a power failure. Connecting the power-fail output (PFO) to the SPEED input reduces clock speed automatically during power-fail events. The integrated reset provides the power-supply monitor- ing functions necessary to ensure correct microcontroller operation. The reset circuit has built-in power-supply transient immunity and provides both power-on reset and power-fail or brownout reset functionality. Two stan- dard factory-trimmed reset levels are available. A power-fail function is provided for power-supply volt- age monitoring and can provide advance notice of an impending power failure. The power-fail input monitors external power-supply voltages through an external resistive divider. Connect PFI to VCC to monitor VCC. Clock Output (CLOCK) The push-pull clock output (CLOCK) drives a ground- connected 1k Ω load or a positive supply connected 500 Ω load to within 300mV of either supply rail. CLOCK remains stable over the full operating voltage range and does not generate short output cycles during either power-on or power-off. A typical startup characteristic is shown in the Typical Operating Characteristics section. The clock output frequency is reduced by a factor of two by taking SPEED low. This functionality allows the microcontroller to operate at reduced power and may be used to extend the time available to perform house- keeping tasks, such as writing data to flash during power failure. Reset The reset function drives the microcontroller reset input to prevent operation in the cases of the initial power-on setting, low power-supply voltages, and the failed watchdog operations. Three reset output versions are available: push-pull RST, push-pull RST, and open-drain RST. The reset timeout period (tRST) is nominally 135s. Power-On Reset (POR) The internal power-on reset (POR) circuit detects the power-supply voltage (VCC) level at startup. The POR circuit starts the oscillator when VCC exceeds the reset rising threshold level (VTH+). The reset output remains asserted from the time VCC crosses the VTH+ and con- tinues to be asserted for the reset timeout period (tRST). Upon completion of the reset timeout, the reset output is released. See Figure 1. Speed-Switching Clock Generator with Power Fail 6 _______________________________________________________________________________________ PIN NAME FUNCTION 1 PFI Power-Fail Input. PFI monitors the condition of either an external supplied voltage or VCC. See the Power Fail section for more details. 2VCC Power Input. Connect VCC to the power supply. Bypass VCC to GND with a 0.1µF capacitor. Install the bypass capacitor as close to the device as possible. 3 N.C. No Connection 4 GND Ground 5 PFO Power-Fail Output. Open-drain output asserts when the voltage being monitored drops below the power-fail threshold voltage. 6 SPEED Clock-Speed Select Input. Connect SPEED high for the factory-trimmed clock output frequency. Connect SPEED low to reduce the clock output frequency by half. 7 RST/RST Reset Output. Reset output is available in one of three configurations: push-pull RST, push-pull RST, or open-drain RST. The reset output occurs if any combination of the following conditions occurs: reset output is asserted during power-up, and whenever VCC is below the reset threshold level; for devices with WDI, reset output asserts when WDI does not receive a rising or falling edge within the watchdog timeout period. 8 CLOCK Clock Output Pin Description |
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