MAX691ACSLASHD datasheet(13/17 Pages) MAXIM

13 / 17 page

Using Separate Power Supplies

for VBATT and VCC

If using separate power supplies for VCC and VBATT,

VBATT must be less than 0.3V above VCC when VCC is

above the reset threshold. As described in the previ-

ous section, if VBATT exceeds this limit and power is

lost at VCC, current flows continuously from VBATT to

VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC

switch until the circuit is broken (Figure 8).

Alternate Chip-Enable Gating

Using memory devices with both CE and CE inputs

allows the CE loop to be bypassed. To do this, con-

nect CE IN to ground, pull up CE OUT to VOUT, and

connect

–CE OUT to the CE input of each memory

device (Figure 10). The CE input of each part then

connects directly to the chip-select logic, which does

not have to be gated.

Adding Hysteresis to the

Power-Fail Comparator

Hysteresis adds a noise margin to the power-fail com-

parator and prevents repeated triggering of PFO when

VIN is near the power-fail comparator trip point. Figure

11 shows how to add hysteresis to the power-fail com-

Microprocessor Supervisory Circuits

______________________________________________________________________________________

MAX691A

MAX693A

MAX800L

MAX800M

VOUT

GND

CE IN

CE OUT

*MAXIMUM Rp VALUE DEPENDS ON

THE NUMBER OF RAMS.

MINIMUM Rp VALUE IS 1k

Ω.

ACTIVE-HIGH

CE LINES

FROM LOGIC

RAM 1

RAM 2

RAM 3

RAM 4

Rp*

MAX691A

MAX693A

MAX800L

MAX800M

VCC

GND

PFI

*OPTIONAL

VIN

+5V

C1*

μP

PFO

VTRIP = 1.25

R1 + R2

VH = 1.25/

R2 I I R3

VL - 1.25 + 5 - 1.25 = 1.25

R1 + R2 I I R3

PFO

VTRIP

VIN

MAX691A

MAX693A

MAX800L

MAX800M

VCC

GND

PFI

+5V

PFO

NOTE: VTRIP IS NEGATIVE.

VTRIP

V-

5 - 1.25

1.25 - VTRIP

V-

Figure 10. Alternate CE Gating

Figure 12. Monitoring a Negative Voltage

Figure 11. Adding Hysteresis to the Power-Fail Comparator

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