LTC6991 datasheet(7/24 Pages) LINER

7 / 24 page

LTC6991

6991f

Output Resistance

vs Supply Current

Typical Start-Up with POL = 1

Typical perForMance characTerisTics

V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.

SUPPLY VOLTAGE (V)

6991 G22

OUTPUT SOURCING CURRENT

OUTPUT SINKING CURRENT

V+

1V/DIV

OUT

1V/DIV

250µs/DIV

V+ = 2.5V

DIVCODE = 15

RSET = 50k

6991 G19

500µs

1µs (tMASTER) WIDE

INITIAL PULSE

pin FuncTions (DCB/S6)

V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-

ply should be kept free from noise and ripple. It should be

bypassed directly to the GND pin with a 0.1µF capacitor.

DIV (Pin 2/Pin 4): Programmable Divider and Polarity

Input. A V+ referenced A/D converter monitors the DIV

pin voltage (VDIV) to determine a 4-bit result (DIVCODE).

VDIV may be generated by a resistor divider between V+

and GND. Use 1% resistors to ensure an accurate result.

The DIV pin and resistors should be shielded from the

OUT pin or any other traces that have fast edges. Limit

the capacitance on the DIV pin to less than 100pF so that

VDIV settles quickly. The MSB of DIVCODE (POL) deter-

mines the polarity of the RST and OUT pins. If POL = 0,

RST is active-high, and forces OUT low. If POL = 1, RST

is active-low and forces OUT high.

SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage

on the SET pin (VSET) is regulated to 1V above GND. The

amount of current sourced from the SET pin (ISET) pro-

grams the master oscillator frequency. The ISET current

range is 1.25µA to 20µA. The output oscillation will stop

if ISET drops below approximately 500nA. A resistor con-

nected between SET and GND is the most accurate way to

set the frequency. For best performance, use a precision

metal or thin film resistor of 0.5% or better tolerance and

50ppm/°C or better temperature coefficient. For lower ac-

curacy applications an inexpensive 1% thick film resistor

may be used.

Limit the capacitance on the SET pin to less than 10pF

to minimize jitter and ensure stability. Capacitance less

than 100pF maintains the stability of the feedback circuit

regulating the VSET voltage.

6991 PF

LTC6991

RST

GND

SET

OUT

V+

DIV

0.1µF

RSET

V+

RST (Pin 4/Pin 1): Output Reset. The behavior of the RST

pin is dependent on the polarity bit (POL). The POL bit is

configuredviatheDIVCODEsetting.WhenPOL=0,setting

RST high forces OUT low and setting RST low allows the

output to oscillate. When POL = 1, RST is active low. In

that case, setting RST low forces OUT high and setting

RST high allows the output to oscillate.

LTC6991 Datasheet(PDF) 7 Page - Linear Technology

LTC6991 Datasheet(HTML) 7 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL