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LIS331DLF Datasheet(PDF) 26 Page - STMicroelectronics |
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LIS331DLF Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 38 page ![]() Register description LIS331DLF 26/38 Doc ID 15101 Rev 4 7.3 CTRL_REG2 (21h) Table 19. Power mode and low-power output data rate configurations PM2 PM1 PM0 Power mode selection Output data rate [Hz] ODRLP 0 0 0 Power-down -- 0 0 1 Normal mode ODR 0 1 0 Low-power 0.5 0 1 1 Low-power 1 1 0 0 Low-power 2 1 0 1 Low-power 5 1 1 0 Low-power 10 Table 20. Normal-mode output data rate configurations and low-pass cut-off frequencies DR1(1) 1. “11” bit configuration is not allowed and may cause incorrect device functionality. DR0(1) Output data rate [Hz] ODR Low-pass filter cut-off frequency [Hz] 00 50 37 01 100 74 1 0 400 292 Table 21. CTRL_REG2 register BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0 Table 22. CTRL_REG2 description BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) HPM1, HPM0 High pass filter mode selection. Default value: 00 (00: normal mode; Others: refer to Table 23) FDS Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) HPen2 High pass filter enabled for interrupt 2 source. Default value: 0 (0: filter bypassed; 1: filter enabled) |
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