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M95128-RMB3P/PC Datasheet(PDF) 6 Page - STMicroelectronics |
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M95128-RMB3P/PC Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 44 page  Description M95128, M95128-W, M95128-R 6/44 Doc ID 5798 Rev 13 1 Description The M95128, M95128-W and M95128-R are electrically erasable programmable memory (EEPROM) devices accessed by a high speed SPI-compatible bus. The memory array is organized as 16384 × 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram Figure 2. SO, UFDFPN and TSSOP connections 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1. AI12805 S VCC M95128 HOLD VSS W Q C D D VSS C HOLD Q SVCC W AI12806 M95128 1 2 3 4 8 7 6 5 |
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