M41ST87YSS6 datasheet(12/52 Pages) STMICROELECTRONICS

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Operating modes

M41ST87Y, M41ST87W

12/52

Doc ID 9497 Rev 8

Operating modes

The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 160 bytes

contained in the device can then be accessed sequentially in the following order:

00h.

Tenths/hundredths of a second register

01h.

Seconds register

02h.

Minutes register

03h.

Century/hours register

04h.

Day register

05h.

Date register

06h.

Month register

07h.

Year register

08h.

Control register

09h.

Watchdog register

0Ah-0Eh. Alarm registers

0Fh.

Flag register

10h-12h.

Reserved

13h.

Square wave

14h.

Tamper register 1

15h.

Tamper register 2

16h-1Dh.

Serial number (8 bytes)

1Eh-1Fh.

Reserved (2 bytes)

20h-9Fh.

User RAM (128 bytes)

The M41ST87Y/W clock continually monitors VCC for an out-of-tolerance condition. Should

VCC fall below VPFD, the device terminates an access in progress and resets the device

address counter. Inputs to the device will not be recognized at this time to prevent erroneous

data from being written to the device from a an out-of-tolerance system. When VCC falls

below VSO, the device automatically switches over to the battery and powers down into an

ultra low current mode of operation to conserve battery life. As system power returns and

VCC rises above VSO, the battery is disconnected, and the device is switched to external

VCC.

Write protection continues until trec (min) elapses after VCC reaches VPFD (min).

For more information on battery storage life refer to application note AN1012.

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