L6730 datasheet(36/52 Pages) STMICROELECTRONICS

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Application details

L6730 - L6730B

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Doc ID 11938 Rev 3

0 dB axis with -20 dB/decade slope and a phase margin greater than 45°. To locate poles

and zeroes of the compensation networks, the following suggestions may be used:

●

Modulator singularity frequencies:

●

Compensation network singularity frequencies:

●

Compensation network design:

–

Put the gain R5/R3 in order to obtain the desired converter bandwidth

–Place

ωZ1 before the output filter resonance ωLC;

–Place

ωZ2 at the output filter resonance ωLC;

–Place

ωP1 at the output capacitor ESR zero ωESR;

–Place

ωP2 at one half of the switching frequency;

–

Check the loop gain considering the error amplifier open loop gain.

Figure 30.

Asymptotic bode plot of converter's open loop gain

Cout

⋅

(13)

Cout

ESR

⋅

(14)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⋅

(15)

⋅

(16)

⋅

(17)

()

⋅

(18)

Vosc

Vin

⋅

(18)

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