GPIOs and LED Drivers

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13

Input Debounce

The MAX7306/MAX7307 sample the input ports every

31ms if input debouncing is enabled for an input port

(D2 = 1 of the port I/O register). The MAX7306/MAX7307

compare each new sample with the previous sample. If

the new sample and the previous sample have the same

value, the corresponding internal register updates.

When the port input is read through the serial interface,

the MAX7306/MAX7307 do not return the instantaneous

backing value of the logic level from the port because

debounce is active. Instead, the MAX7306/MAX7307

return the stored debounced input signal.

When debouncing is enabled for a port input, transition

detection applies to the stored debounced input signal

value, rather than to the instantaneous value at the

input. This process allows for useful transition detection

of noisy signals, such as keyswitch inputs, without

causing spurious interrupts.

Port Input Transition Detection and Interrupt

Any transition on ports configured as inputs automatically

set the D1 bit of that port’s I/O registers high. Any input can

be selected to assert an interrupt output indicating a transi-

tion has occurred at the input port(s). The MAX7306/

MAX7307 sample the port input (internally latched into a

snapshot register) during a read access to its port P_ I/O

register. The MAX7306/MAX7307 continuously compare

the snapshot with the port’s input condition. If the device

detects a change for any port input, an internal transition

flag sets for that port. Read register 0x26 to clear the inter-

rupt, then read all the port I/O registers (0x01 to 0x04) by

initiating a burst read to clear the MAX7306/MAX7307’s

internal transition flag. Note that when debouncing is

enabled for a port input, transition detection applies to the

stored debounced input signal value, rather than to the

instantaneous value at the input. Transition bits D4 and

D3 of port registers must be set to 0 to detect the next

rising or falling edge on the input port (P_).

The MAX7306/MAX7307 allow the user to select the

input port(s) that cause an interrupt on the INT output.

Set INT for each port by using the INT enable bit (bit

D5) in each port P_ register. The appropriate port’s

transition flag always sets when an input changes,

regardless of the port’s INT enable bit settings. The INT

enable bits allow processor interrupt only on critical

events, while the inputs and the transition flags can be

polled periodically to detect less critical events. When

debounce is disabled, a signal transition between the

9th and 11th falling edges of the clock will not be regis-

tered, since the transition is detected and cleared at

the same time.

Ports configured as outputs do not feature transition

detection, and therefore, cannot cause an interrupt.

The INT output never reasserts during a read sequence

because this process could cause a recursive reentry

into the interrupt service routine. Instead, if a data

change occurs during the read that would normally set

the INT output, the interrupt assertion is delayed until

the STOP condition. If the changed input data is read

before the STOP condition, a new interrupt is not

required and not asserted. The INT bit and INT output

(if selected) have the same value at all times.

Transition Flag

The transition bit in device configuration register 0x26 is

a NOR of all the port I/O registers’ individual transition

bits. A port’s I/O register’s transition bit sets when that

port is set as an input, and the input changes from the

port’s I/O registers last read through the serial interface.

A port’s individual transition bit clears by reading that

port’s I/O register. Always write a 0 to bits D4 and D3 of

the configuration register 0x26 to properly configure a

transition detection. The transition flag of configuration

register 0x26 is only cleared after reading all ports I/O

registers on which a transition has ocurred.

RST Input

The active-low RST input operates as a hardware reset

MAX7306/MAX7307

(this

feature

allows

the

MAX7306/MAX7307 supply current to be minimized in

power-critical applications by effectively disconnecting

the MAX7307 from the bus). RST also operates as a

chip enable, allowing multiple devices to use the same

its RST input high at any time. RST can be configured

to restore all port registers to the power-up settings by

setting bit D0 of device configuration register 0x26

(Table 1). RST can also be configured to reset the inter-

nal timing counters used for PWM and blink by setting

bit D1 of device configuration register 0x26.

When RST is low, the MAX7306/MAX7307 are forced

clear the interrupt output INT.

INT Output

Port P1 can be configured as a latching interrupt out-

put, INT, that flags any transients on any combination of

selected ports configured as inputs. Any transitions

occurring at the selected inputs assert INT low to alert