STM32F103C8 datasheet(61/96 Pages) STMICROELECTRONICS

61 / 96 page

STM32F103x8, STM32F103xB

Electrical characteristics

Doc ID 13587 Rev 12

61/96

Output voltage levels

Unless otherwise specified, the parameters given in Table 35 are derived from tests

performed under ambient temperature and VDD supply voltage conditions summarized in

Table 9. All I/Os are CMOS and TTL compliant.

Table 35.

Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

VOL

(1)

The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

TTL port

IIO = +8 mA

2.7 V < VDD < 3.6 V

0.4

VOH

(2)

The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

VDD–0.4

VOL

(1)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

CMOS port

IIO =+ 8mA

2.7 V < VDD < 3.6 V

0.4

VOH

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

2.4

VOL

(1)(3)

Based on characterization data, not tested in production.

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

IIO = +20 mA

2.7 V < VDD < 3.6 V

1.3

VOH

(2)(3)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

VDD–1.3

VOL

(1)(3)

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

IIO = +6 mA

2 V < VDD < 2.7 V

0.4

VOH

(2)(3)

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

VDD–0.4

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