R29 datasheet(49/473 Pages) RENESAS

49 / 473 page

R8C/28 Group, R8C/29 Group

5. Resets

Rev.2.10

Sep 26, 2008

Page 30 of 441

REJ09B0279-0210

5.3

Voltage Monitor 0 Reset (N, D Version)

A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input

voltage to the VCC pin. The voltage to monitor is Vdet0.

When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.

When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock

start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”

and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip oscillator clock divided by 8 is

automatically selected as the CPU clock after reset.

The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset. Setting the LVD0ON

bit is only valid after a hardware reset.

To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register

to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register

to 1.

The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset

enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh

using a flash programmer.

Refer to Figure 5.5 OFS Register for details of the OFS register.

Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.

The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while

writing to the internal RAM is in progress, the contents of internal RAM are undefined.

Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.

5.4

Voltage Monitor 1 Reset (N, D Version)

A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input

voltage to the VCC pin. The voltage to monitor is Vdet1.

When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a

program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip

oscillator clock divided by 8 is automatically selected as the CPU clock.

The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for

details.

The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while

writing to the internal RAM is in progress, the contents of internal RAM are undefined.

Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.

5.5

Voltage Monitor 1 Reset (J, K Version)

A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input

voltage to the VCC pin. The voltage to monitor is Vdet1.

When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset.

When the input voltage to the VCC pin reaches the Vdet1 level or above, the low-speed on-chip oscillator clock

start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”

and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip oscillator clock divided by 8 is

automatically selected as the CPU clock after reset.

The LVD1ON bit in the OFS register can be used to enable or disable voltage monitor 1 reset. Setting the LVD1ON

bit is only valid after a hardware reset.

To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register

to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register

to 1.

The LVD1ON bit cannot be changed by a program. To set the LVD1ON bit, write 0 (voltage monitor 1 reset

enabled after hardware reset) or 1 (voltage monitor 1 reset disabled after hardware reset) to bit 6 of address 0FFFFh

using a flash programmer.

Refer to Figure 5.5 OFS Register for details of the OFS register.

Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset.

The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while

writing to the internal RAM is in progress, the contents of internal RAM are undefined.

Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.

R29 Datasheet(PDF) 49 Page - Renesas Technology Corp

R29 Datasheet(HTML) 49 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL