R8C23 datasheet(12/54 Pages) RENESAS

12 / 54 page

R8C/22 Group, R8C/23 Group

2. Central Processing Unit (CPU)

Rev.2.00 Aug 20, 2008

Page 10 of 48

REJ03B0097-0200

Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB

comprise a register bank. Two sets of register banks are provided.

Figure 2.1

CPU Registers

b31

b15

b8b7

Data registers(1)

Address registers(1)

R0H(high-order of R0)

INTBH

b15

b19

INTBL

Frame base registers(1)

The 4-high order bits of INTB are INTBH and

the 16-low order bits of INTB are INTBL.

Interrupt table register

b19

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG

Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

IPL

b15

NOTE:

1. A register bank comprises these registers. Two sets of register banks are provided.

R0L (low-order of R0)

R1H(high-order of R1) R1L (low-order of R1)

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