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IFX24401 Datasheet(PDF) 5 Page - Infineon Technologies AG |
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IFX24401 Datasheet(HTML) 5 Page - Infineon Technologies AG |
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5 / 18 page ![]() IFX24401 Pin Configuration Data Sheet 5 Rev. 1.02, 2009-12-10 Figure 3 Pin Configuration PG-SSOP-14 (top view) 3.2 Pin Definitions and Functions (PG-SSOP-14 ) Pin Symbol Function 1,2,3,5,7 N.C. No Connect May be open or connected to GND 4GND Ground 6EN Enable Input Low signal level disables the regulator. Pull-down resistor is integrated. 8,10,11,1 2,14 N.C. No Connect May be open or connected to GND 9Q Output Place capacitor between Q pin and GND. Capacitor placement should be close to pin. Refer to capacitance and ESR requirements in “Functional Range” on Page 6 13 I Input Connect ceramic capcitor between I and GND Pad Exposed Pad Connect to board GND and heatsink |
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