IR3508

Page 13 of 19

October 27, 2008

PSI_SYNC

PSI

8 PHSIN Delay

D_PWM LATCH

CLK

Figure 7: PSI assertion.

Debugging Mode

If the CSIN+ pin is pulled up to VCCL voltage, IR3508 enters into debugging mode. Both drivers are pulled low

and IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases.

However, the phase timing from PHSIN to PHSOUT does not change.

Emulated Bootstrap Diode

IR3508 integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at higher

switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be needed.

AFTER

OVP

FAULT

LATCH

130mV

OUTPUT

VOLTAGE

(VO)

OVP

THRESHOLD

VCCL-800 mV

OVP CONDITION

NORMAL OPERATION

IOUT(ISHARE)

GATEL

(PHASE IC)

GATEH

(PHASE IC)

VDAC

ERROR

AMPLIFIER

OUTPUT

(EAOUT)

Figure 8: Over-voltage protection waveforms