MSC8102UG datasheet(2/80 Pages) FREESCALE

2 / 80 page

MSC8102, Rev. 12

Freescale Semiconductor

Table of Contents

Features ............................................................................................................................................................... iv

Product Documentation ......................................................................................................................................ix

Chapter 1

Signals/Connections

1.1

Power Signals ...................................................................................................................................................1-3

1.2

Clock Signals ....................................................................................................................................................1-3

1.3

Reset and Configuration Signals.......................................................................................................................1-3

1.4

Direct Slave Interface, System Bus, and Interrupt Signals ...............................................................................1-4

1.5

Memory Controller Signals ............................................................................................................................1-10

1.6

GPIO, TDM, UART, and Timer Signals.........................................................................................................1-12

1.7

EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-18

1.8

Reserved Signals.............................................................................................................................................1-19

Chapter 2

Specifications

2.1

Maximum Ratings.............................................................................................................................................2-1

2.2

Recommended Operating Conditions ...............................................................................................................2-2

2.3

Thermal Characteristics ....................................................................................................................................2-2

2.4

DC Electrical Characteristics............................................................................................................................2-3

2.5

AC Timings.......................................................................................................................................................2-4

Chapter 3

Packaging

3.1

FC-CBGA (HCTE) Package Description .........................................................................................................3-1

3.2

FC-CBGA (HCTE) Package Mechanical Drawing ........................................................................................3-19

Chapter 4

Design Considerations

4.1

Power Supply Design and Layout Considerations............................................................................................4-1

4.2

Connectivity Guidelines ...................................................................................................................................4-3

4.3

Recommended Clock Connections for Single-Master Mode with DLL Off ....................................................4-4

4.4

Power Considerations .......................................................................................................................................4-5

4.5

Thermal Design Considerations........................................................................................................................4-6

Data Sheet Conventions

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

VIL/VOL

False

Deasserted

VIH/VOH

True

Asserted

VIH/VOH

False

Deasserted

VIL/VOL

Note:

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

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