MPC8377E datasheet(124/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

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Freescale Semiconductor

Document Revision History

27 Document Revision History

Table 87 provides a revision history for this hardware specification.

Table 87. Document Revision History

Revision

Date

Substantive Change(s)

11/2010

• In Table 25, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.

•In Table 40, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR.

•In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 23, “Clocking,” updated LCCR

to LCRR.

•In Table 72, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and

TEST_SEL1 pins—no change in functionality.

03/2010

• Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”

•In Table 34, “USB DC Electrical Characteristics,” and Table 35, “USB General Timing Parameters (ULPI

Mode Only),” added table footnotes .

•In Table 39, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 40, “Local Bus

General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.

•In Figure 22, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and

Figure 24, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted

“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.

•In Figure 63, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added

heat spreader.

•In Section 25.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list

of open drain type pins.

•In Table 72, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and

AVDD_P pins.

•in Table 72, “TePBGA II Pinout Listing,” added Note 16 to eTSEC pins.

•In Table 77, “CSB Frequency Options for Host Mode,” and Table 78, “CSB Frequency Options for Agent

Mode,” updated csb_clk frequencies available.

•In Table 84, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”

10/2009

• In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.

•In Table 5, “MPC8378E Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.

•In Table 5, “MPC8378E Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.

•In Table 5, “MPC8378E Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.

•In Table 11, removed overbar from CFG_CLKIN_DIV.

•In Table 17, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1

and DDR2 to 600 and 400

μA, respectively. Also, updated Note 1 and added Note 2.

•In Table 20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to

“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.

•In Table 20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 21, “DDR1 and

DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.

•In Table 29, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.

•In Table 60, Gen 1i/1.5G Transmitter AC Specifications,” and Table 62, Gen 2i/3G Transmitter AC

Specifications,” corrected titles from “Transmitter” to “Receiver”.

•In Table 72, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V

to VDD pin.

•In Table 74, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”

range to 125–200.

•In Table 79, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.

•In Table 80, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .

•In Section 20.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,

respectively.

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