ISL6366IRZ datasheet(39/44 Pages) INTERSIL

39 / 44 page

ISL6366

FN6964.0

January 3, 2011

MULTIPHASE RMS IMPROVEMENT

Figure 32 is provided as a reference to demonstrate the dramatic

reductions in input-capacitor RMS current upon the

implementation of the multiphase topology. For example,

compare the input RMS current requirements of a 2-phase

converter versus that of a single phase. Assume both converters

have a duty cycle of 0.25, maximum sustained output current of

40A, and a ratio of IL,PP to IO of 0.5. The single phase converter

would require 17.3ARMS current capacity while the 2-phase

converter would only require 10.9ARMS. The advantages become

even more pronounced when output current is increased and

additional phases are added to keep the component cost down

relative to the single phase approach.

Layout and Design Considerations

The following layout and design strategies are intended to minimize

the noise coupling, the impact of board parasitic impedances on

converter performance and to optimize the heat-dissipating

capabilities of the printed-circuit board. These sections highlight

some important practices which should follow during the layout

process. A layout check list in excel format is available for use.

Pin Noise Sensitivity, Design and Layout

Consideration

Table 14 shows the noise sensitivity of each pin and their design

and layout consideration. All pins and external components

should not be across switching nodes and placed in general

proximity to the controller.

TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION

PIN NAME

NOISE

SENSITIVITY

DESCRIPTION

NC4

Open Pin. Reserved for “ISENIN-” in

ISL6366A/67: It will be noise sensitive and

connect to input supply side of the input

inductor or resistor pin with L/DCR or

ESL/R matching network in close

proximity to the controller. Place NTC in the

close proximity to input inductor for

thermal compensation.

FIGURE 32. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR SINGLE-PHASE CONVERTER

00.4

1.0

0.2

0.6

0.8

DUTY CYCLE (VOUT/VIN)

0.6

0.2

0.4

IL,PP = 0

IL,PP = 0.5 IO

IL,PP = 0.75 IO

NC5

Open Pin. Reserved for “ISENIN+” in

ISL6366A/67: It will be noise sensitive and

connects to the Drain of High-side MOSFET

side of the input inductor or resistor pin.

EN_PWR

There is an internal 1µs filter. Decoupling

capacitor is NOT needed, but if needed,

use a low time constant one to avoid too

much of shut-down delay. It will also be the

output of CFP function in ISL6366A and

ISL6367: 34

Ω strong pull-up. 25 mils

spacing from other traces.

RAMP_ADJ

Yes

NO decoupling capacitor allowed on this

pin, but decoupling its resistor pull-up RAIL

with a high quality ceramic capacitor

(0.1µF or higher) or with very small RC

filter (<2.2µs).

RGND

Yes

Pairing up with the positive rail remote

sensing line that connected to FB resistor,

and routing them to the load sensing

points.

VSEN

Used for Overvoltage protection sensing

only, and it has 1µs internal filter.

Decoupling is NOT needed. Add a 0Ω series

impedance to be compatible with

ISL6366A/67.

Yes

Pairing up with the negative rail of remote

sensing line that connected to RGND, and

routing them to the load sensing points.

Reserve an RC from FB to GND to

compensate the output lagging from DAC

during DVID transitions.

HFCOMP

Yes

Connect an R to the VR0 output. The R

value is typically equal or slightly higher

than the feedback resistor (droop resistor),

fine tuned according to the high frequency

transient performance. Placing the

compensation network in close proximity

to the controller.

PSICOMP

Yes

The series impedance typically should be

2x-3x the impedance in type III

compensation to reduce noise coupling.

Placing the compensation network in close

proximity to the controller.

COMP

Yes

Placing the compensation network in close

proximity to the controller. Typically use a

68pF or higher across FB to COMP

depending upon the noise coupling of the

layout.

DVC

Yes

4/3 of DAC voltage. Placing the

compensation network in close proximity

to the controller.

IMON

Yes

Referring to GND, not RGND. Place R and C

in general proximity to the controller. The

time constant of RC should be sufficient,

typically 1ms, as an average function for

the digital IOUT of VR0.

TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION

(Continued)

PIN NAME

NOISE

SENSITIVITY

DESCRIPTION

ISL6366IRZ Datasheet(PDF) 39 Page - Intersil Corporation

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