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CMX615P3 Datasheet(PDF) 22 Page - CML Microcircuits

Part # CMX615P3
Description  Digital Line to POTS Interface
PDF  26 Pages
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Manufacturer  CMLMICRO [CML Microcircuits]
Direct Link  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

CMX615P3 Datasheet(HTML) 22 Page - CML Microcircuits

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Digital Line to POTS Interface
CMX615
© 1999 Consumer Microcircuits Limited
22
D/615/4
1.7.1.3 Operating Characteristics
For the following conditions unless otherwise specified:
VDD = 2.7V at Tamb = 25°C and VDD = 3.0V to 5.5V at Tamb = -40 to +85°C,
Xtal Frequency = 3.579545MHz
± 0.1%
0dBm corresponds to 775mVrms.
DC Parameters
Notes
Min.
Typ.
Max.
Unit
I
DD
Zero-Power Mode
1, 2
-
<1.0
-
µA
OpAmp only Enabled, V
DD = 5.0V
1
-
1.5
-
mA
OpAmp only Enabled, V
DD = 3.3V
1
-
0.75
-
mA
All Enabled, V
DD = 5.0V
1
-
5.0
7.5
mA
All Enabled, V
DD = 3.3V
1
-
3.0
4.5
mA
Logic ‘1’ Input Level
3
70%
-
-
V
DD
Logic ‘0’ Input Level
3
-
-
30%
V
DD
Logic Input Leakage Current (Vin = 0 to V
DD),
3
-1.0
-
+1.0
µA
(excluding XTAL/CLOCK input)
Output Logic ‘1’ Level (I
OH = 360µA)
V
DD-0.4
-
-
V
Output Logic ‘0’ Level (I
OL = 360µA)
-
-
0.4
V
IRQN O/P ‘Off State Current (V
OUT = VDD)
-
-
1.0
µA
FSK Encoder and Tx UART
Notes
Min.
Typ.
Max.
Unit
Level at TONEFSK pin
4
-1.0
0.0
1.0
dBm
Twist (Mark level WRT Space level)
-2.0
0
+2.0
dB
Tx 1200bits/sec (V23 mode)
Baud Rate (set by UART and Xtal frequency)
1194
1200
1206
Baud
Mark (Logical 1) Frequency
1297
1300
1303
Hz
Space (Logical 0) Frequency
2097
2100
2103
Hz
Tx 1200bits/sec (Bell 202 mode)
Baud Rate (set by UART and Xtal frequency)
1194
1200
1206
Baud
Mark (Logical 1) Frequency
1197
1200
1203
Hz
Space (Logical 0) Frequency
2197
2200
2203
Hz
TONEFSK Signal Level
Notes
Min.
Typ.
Max.
Unit
Level at TONEFSK pin for:
Single tone
4
-1.0
0
1.0
dBm
Dual tone (per tone)
4
-4.0
-3.0
-2.0
dBm
DTMF High Frequency Group
4
-4.0
-3.0
-2.0
dBm
DTMF Low Frequency Group
4
-6.0
-5.0
-4.0
dBm
Output Impedance
-
10.0
-
k
Ω
Tone frequency resolution
-2.0
-
2.0
Hz
Tone output distortion
5
-
0.8
-
%
Notes:
1.
At 25
°C, not including any current drawn from the CMX615 pins by external circuitry other
than X1, C1 and C2.
2.
All logic inputs at VSS except for CSN input which is at VDD.
3.
Excluding XTAL/CLOCK pin.
4.
At VDD = 5.0V, load resistance greater than 40kΩ, signal levels are proportional to VDD.
5.
Frequency above 300Hz.
6.
SPM has a soft rise and fall time of about 4.5ms. The level changes between V
BIAS and 0dBm
in 2dB steps, 16 steps per rise and fall. When SPM is disabled, an extra 4.5ms falling tail end
of signal should be taken into consideration.



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