MX-COM, INC.

Page 3

MX118

MX118

MX118

MX118

MX118

Pin Function Chart

Pin Function Chart

Pin Function Chart

Pin Function Chart

Pin Function Chart

Pin

Pin

Pin

Pin

Pin

Function

Function

Function

Function

Function

1

Xtal:

Xtal:

Xtal:

Xtal:

Xtal: This is the output of the clock oscillator inverter.

2

No Connection.

3

C1 Filter Output:

C1 Filter Output:

C1 Filter Output:

C1 Filter Output:

C1 Filter Output: This is the output of the channel 1 input filter. It should be coupled to pin 4 (C1

Balanced Modulator Input) by a 1.0

µF cap. See Figure 3.

4

C1 Balanced Modulator Input:

C1 Balanced Modulator Input:

C1 Balanced Modulator Input:

C1 Balanced Modulator Input:

C1 Balanced Modulator Input: This is the input to the channel 1 balanced modulator. Internally

biased at V

DD

/2, it should be coupled to pin 3 (C1 Filter Output) by capacitor C

2

.

5

V

V

V

V

V

SS

SS

SS

SS

:::: Negative supply (GND).

6

C1 Output:

C1 Output:

C1 Output:

C1 Output:

C1 Output: This is the analog output of channel 1. It is internally biased at V

DD

/2.

7

C1 Gain Amp Output:

C1 Gain Amp Output:

C1 Gain Amp Output:

C1 Gain Amp Output:

C1 Gain Amp Output: This is the output pin of the channel 1 gain adjusting op-amp. See Figure 4

for test gain setting components.

8

C1 Input:

C1 Input:

C1 Input:

C1 Input:

C1 Input: This is the analog signal input to channel 1. This input is to a gain adjusting op-amp whose

gain is set by internal components. See Figure 4.

9

C2 Input:

C2 Input:

C2 Input:

C2 Input:

C2 Input: This is the analog signal input to channel 2. This input is to a gain adjusting op-amp whose

gain is set by internal components. See Figure 4.

10

C2 Gain Amp Output:

C2 Gain Amp Output:

C2 Gain Amp Output:

C2 Gain Amp Output:

C2 Gain Amp Output: This is the output pin of the channel 2 gain adjusting op-amp. See Figure 4

for test gain setting components.

11

C2 Output:

C2 Output:

C2 Output:

C2 Output:

C2 Output: This is the analog output of channel 2. It is internally biased at V

DD

/2.

12

V

V

V

V

V

BIAS

BIAS

BIAS

BIAS

:::: This is the analog bias line at V

DD

/2. It should be coupled to V

SS

by a 1.0

µF or greater

capacitor. See Figure 3.

13

C2 Balanced Modulator Input:

C2 Balanced Modulator Input:

C2 Balanced Modulator Input:

C2 Balanced Modulator Input:

C2 Balanced Modulator Input: This is the input to the channel 2 balanced modulator. Internally

biased at V

DD

/2, it should be coupled to pin 14 (C2 Filter Output) by capacitor C

7

.

14

C2 Filter Output:

C2 Filter Output:

C2 Filter Output:

C2 Filter Output:

C2 Filter Output: This is the output of the channel 1 input filter. It should be coupled to pin 13 (C2

Balanced Modulator Input) by a 1.0

µF capacitor. See Figure 3.

15

V

V

V

V

V

DD

DD

DD

DD

:::: Positive supply of 3.0 V to 5.5 V.

16

Xtal/Clock:

Xtal/Clock:

Xtal/Clock:

Xtal/Clock:

Xtal/Clock: 4.433619 MHz or an externally derived clock is injected at this pin. (See Figure 3.)