LC75412 datasheet(13/21 Pages) SANYO

13 / 21 page

No. 7053-13/21

LC75412E, 75412W

Pin Name

Pin No.

Function

Equivalent circuit

Continued from preceding page.

• Fader output pins. Attenuation is possible separately for the front

end and rear end. The attenuation amount is the same for L and

LFOUT

LROUT

RFOUT

RROUT

VDD

• Connect a capacitor of a few tens of µF between Vref and AVSS

(VSS) as a VDD/2 voltage generator, current ripple

countermeasure.

Vref

VDD

LVref

RVref

• External muting control pin

• Setting this pin to VSS level sets forcibly fader volume block to

–

∞ level.

MUTE

VDD

• Timer pin when there is no signal in the zero-cross circuit.

Forcibly set data when there is no zero-cross signal, from the time

the data is set until the timer ends.

TIM

VDD

• Input pin for serial data and clock used for control

VDD

• Chip enable pin. Data is written to the internal latch and the analog

switches are operated when the level changes from High to Low.

Data transfer is enabled when the level is High.

• Analog system ground pins

LAVSS

RAVSS

• Power supply pin

VDD

• Logic system ground pin

DVSS

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