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CY14B256KA Datasheet(PDF) 21 Page - Cypress Semiconductor |
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CY14B256KA Datasheet(HTML) 21 Page - Cypress Semiconductor |
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21 / 27 page ![]() CY14B256KA Document #: 001-55720 Rev. *C Page 21 of 27 Software Controlled STORE/RECALL Cycle Parameter[30, 31] Description 25 ns 45 ns Unit Min Max Min Max tRC STORE/RECALL initiation cycle time 25 – 45 – ns tSA Address setup time 0–0– ns tCW Clock pulse width 20 – 30 – ns tHA Address hold time 0–0– ns tRECALL RECALL duration – 200 – 200 µs tSS [32, 33] Soft sequence processing time – 100 – 100 µs Switching Waveforms Figure 12. CE & OE Controlled Software STORE/RECALL Cycle [31] Figure 13. AutoStore Enable/Disable Cycle t RC t RC t SA t CW tCW t SA tHA t LZCE t HZCE tHA t HA t HA t STORE/tRECALL t HHHD tLZHSB High Impedance Address #1 Address #6 Address CE OE HSB(STOREonly) DQ (DATA) RWI tDELAY Note 34 t RC t RC t SA t CW t CW t SA tHA tLZCE t HZCE t HA t HA t HA t DELAY Address #1 Address #6 Address CE OE DQ (DATA) t SS Note 34 Notes 30. The software sequence is clocked with CE controlled or OE controlled reads. 31. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles. 32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 33. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 34. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. [+] Feedback |
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