CY23FP12-002

Document #: 38-07644 Rev. *B

Page 9 of 14

Switching Characteristics [5]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Reference frequency[6]

10

–

200

MHz

Reference edge rate

1

–

–

V/ns

Reference duty cycle

25

–

75

%

Output frequency[7]

10

–

200

MHz

10

–

100

Output duty cycle[5]

45

50

55

%

40

50

60

Rise time[5]

––

1.6

ns

––

0.8

––

2.0

––

1.0

Fall time[5]

––

1.6

ns

––

0.8

––

1.6

––

0.8

TTB

Total timing budget,[8,9]

Bank A and B same

frequency

Outputs at 200 MHz, tracking skew not

included

–

–

650

ps

Total timing budget, bank A

and B different frequency

–

–

850

Output-to-output skew[5]

All outputs equally loaded

–

–

200

ps

Bank-to-bank skew

Same frequency

–

–

200

Bank-to-bank skew

Different frequency

–

–

400

Bank-to-bank skew

Different voltage, same frequency

–

–

400

Input-to-output skew (static

phase offset)[5]

–

0

250

ps

Device-to-device skew[5]

–

0

500

ps

Cycle-to-cycle jitter[5]

(Peak-to-peak)

Bank A and B same frequency

–

–

200

ps

Cycle-to-cycle jitter[[5]

(Peak-to-peak)

Bank A and B different frequency

–

–

400

Notes

5. All parameters are specified with loaded outputs.

6. When the device is configured as a non-PLL fanout buffer (PLL Power down enabled), the reference frequency can be lower than 10MHz. With auto power down

disabled and PLL power down enabled, the reference frequency can be as low as DC level.

7. When the device is configured as a non-PLL fanout buffer (PLL Power down enabled), the output frequency can be lower than 10MHz. With auto power down

disabled and PLL power down enabled, the output frequency can be as low as DC level.

8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,

operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,

cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.

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