CY8C32 datasheet(28/119 Pages) CYPRESS

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PSoC® 3: CY8C32 Family

Data Sheet

Document Number: 001-56955 Rev. *J

Page 28 of 119

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 50 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The accuracy of the

PLL output depends on the accuracy of the PLL input source.

The most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate to generate the CPU and system clocks

up to the device’s maximum frequency.

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO or DSI (external pin). The PLL clock source can be

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low-power modes.

6.1.1.4 Internal Low-Speed Oscillator

The ILO provides clock frequencies for low-power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

The 1 kHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low-power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW).

The central timewheel is a 1 kHz, free running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled,

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic

interrupts for timing purposes or to wake the system from a

low-power mode. Firmware can reset the central timewheel.

Systems that require accurate timing should use the RTC

capability instead of the central timewheel.

The 100-kHz clock (CLK100K) works as a low-power system

clock to run the CPU. It can also generate time intervals such as

fast sleep intervals using the fast timewheel.

The fast timewheel is a 100-kHz, 5-bit counter clocked by the ILO

that can also be used to wake the system. The fast timewheel

settings are programmable, and the counter automatically resets

when the terminal count is reached. This enables flexible,

periodic wakeups of the CPU at a higher rate than is allowed

using the central timewheel. The fast timewheel can generate an

optional interrupt each time the terminal count is reached.

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

6.1.2 External Oscillators

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see

“Phase-locked Loop” section on page 27). The GPIO pins

connecting to the external crystal and capacitors are fixed.

MHzECO accuracy depends on the crystal chosen.

Figure 6-2. MHzECO Block Diagram

6.1.2.2 32.768-kHz ECO

The 32.768-kHz External Crystal Oscillator (32kHzECO)

provides precision timing with minimal power consumption using

an external 32.768-kHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1-second interrupt to

implement the RTC functionality in firmware.

The oscillator works in two distinct power modes. This allows

users to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

Figure 6-3. 32kHzECO Block Diagram

6.1.2.3 Digital System Interconnect

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and Universal

Digital Blocks.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

(Pin P15[0])

4 - 25 MHz

Crystal Osc

XCLK_MHZ

4 – 25 MHz

crystal

Capacitors

External

Components

(Pin P15[1])

(Pin P15[2])

32 kHz

Crystal Osc

XCLK32K

32 kHz

crystal

Capacitors

External

Components

(Pin P15[3])

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